STL仕様下での論理依存追跡による高速制約抽出と修正制御
Fast Constraint Extraction for Corrective Control under STL Specifications via Logical Dependency Tracking
Signal Temporal Logic仕様の不確実性下での充足を保証するため、論理依存追跡で不確実性を伝播させ、十分制約のDNFを高速抽出し、最小努力の制御修正を線形計画で実現する手法を提案。
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著者: Antoine Besset, Joris Tillet, Chuchu Fan, Julien Alexandre dit Sandretto
分類: cs.LO, cs.RO, eess.SY
原文アブストラクト
Ensuring the satisfaction of Signal Temporal Logic (STL) specifications under uncertainty is challenging, as reachability-based monitoring provides guarantees but does not indicate how to restore satisfaction when it becomes indeterminate. A key difficulty is identifying which uncertain components actually affect global satisfaction, especially for nested formulas. This paper introduces a logical dependency tracking framework that propagates uncertainty through the STL structure and captures the causal contribution of reachable sets to satisfaction. By associating markers to uncertain predicates and propagating them via three-valued semantics, we extract in milliseconds a compact Disjunctive Normal Form (DNF) of sufficient constraints, avoiding combinatorial enumeration. As an application, we formulate control correction as a minimum-effort optimization problem. Using zonotopic reachability, the derived constraints are enforced via linear programming, yielding corrections that guarantee STL satisfaction under bounded uncertainty and provide certified probabilistic bounds in the stochastic case. We demonstrate the approach on a nonlinear system with nested STL specifications, showing that dependency tracking enables efficient and formally guaranteed correction. The tracking implementation is available at https://github.com/Antoine-Bst/STL-Three-Valued-Clause-Filtering/.